Future-Ready,
Open Architecture
Controllers
Because they’re built on an open-architecture platform, Mercury controllers let you integrate disparate systems into one unified solution, making them the best-in-class backbone of any access control system.
Meet the All-New Mercury MP Intelligent Controllers
- Open Architecture that provides the freedom to choose best of breed software providers – today and in the future
- Business Continuity through supply chain options that provide dual footprint circuit designs with alternate components
- Latest Cybersecurity including ARM TrustZone, secure boot CPU and latest crypto
- Expanded Development through a future-ready app development environment
The MP controller’s legacy mode feature provides backward compatibility with existing LP controllers to make the transition as smooth as possible. Host access control system software doesn’t need to be changed for LP native setups. We also designed MP controllers to be compatible with all Series 3 (red) and Series 2/1 (green) IO modules, so you can easily replace existing LP controllers with MP controllers and connect to previously installed IO modules.
MP controllers will be available later in 2024. Please contact your Mercury OEM partner for availability and compatibility with existing deployments and new opportunities.
As we introduce the new Mercury MP Intelligent Controllers, we recognize that our customers are at various stages in their technology lifecycle, which is why we created a Migration Guide. The guide can help you understand the migration pathways and priorities for Mercury controllers and IO modules. Download our Migration Guide.
MercOS: Next-Generation Firmware
Our all-new, next-generation firmware platform, MercOS, is supported by both the LP and MP controllers. Powered by a uniform build environment, the firmware’s upgraded operating system drives a streamlined release cycle governed by cyber policies, with analysis and auditing at the forefront of every release. This revolutionary platform ensures the LP controllers will be fully supported with new feature enhancements, bug fixes and cyber security updates through 2028.
Access Security Controllers FAQ
The timing requirements for the downstream RS-485 communication bus are very critical and expect a quick turn around time. The timing of replies/packets sent on an Ethernet connection can introduce additional latency and potentially impact communications negatively where quick turn around times are expected.
Mercury currently has not tested or approved any RS-485 to Ethernet converters to be used for downstream communications.
A total of 16 card formats exist on the controller. If using the Asset Management functionality then the upper 8 card formats are used for assets and the lower 8 card formats can be used for access control. If asset management is not being used, then all 16 card formats can be used for access control. Consult your OEM provider for more information on asses management.
Note: Only the lower 8 card formats are currently sent to the SIO modules to be used in degraded (offline) mode for facility code only.
Following are the memory specs for the LP Series controllers.
Two (2) 32M x 16 (64 Mbyte) DDR2 SDRAM (total 128 Mbyte)
One (1) eMMC NAND Flash 2 GByte
One (1) SPI Serial Flash 32 Mbit (4 MByte)
One (1) 512K x 16 SRAM (1 Mbyte) with battery backup
One (1) I2C Crypto EEPROM 32 Kbit for secure key storage
Two (2) 32M x 16 (64 Mbyte) DDR2 SDRAM (total 128 Mbyte)
One (1) eMMC NAND Flash 4 GByte
One (1) SPI Serial Flash 32 Mbit (4 MByte)
One (1) 512K x 16 SRAM (1 Mbyte) with battery backup
One (1) I2C Crypto EEPROM 32 Kbit for secure key storage
Two (2) 32M x 16 (64 Mbyte) DDR2 SDRAM (total 128 Mbyte)
One (1) eMMC NAND Flash 4 GByte
One (1) SPI Serial Flash 32 Mbit (4 MByte)
One (1) 512K x 16 SRAM (1 Mbyte) with battery backup
One (1) I2C Crypto EEPROM 32 Kbit for secure key storage
Two (2) 128M x 16 (256 Mbyte) DDR2 SDRAM (total 512 MByte)
One (1) eMMC NAND Flash 4 GByte
One (1) SPI Serial Flash 32 Mbit (4 MByte)
One (1) 512K x 16 SRAM (1 MByte) with battery backup
One (1) I2C Crypto EEPROM 32 Kbit for secure key storage
The bulk erase process for 1.x EP/LP firmware is:
- Configure Dip Switch 1 and 2 ON and 3 and 4 OFF
- Power up panel
- Within a few seconds LEDs 1 & 2 and 3 & 4 to alternately flash ON/OFF
- Within 10 seconds after the above pattern starts, change switch 1 to OFF
- All LED's will be off for several seconds seconds and then LEDs 1 & 4 will flash for about 3 seconds indicating the erase process has completed.
The bulk erase process for 2.x firmware is the same as 1.x with the difference there are longer wait times in-between steps:
- Configure Dip Switch 1 and 2 ON and 3 and 4 OFF
- Reset/Apply power to the panel. LED 1 will flash on for 55 seconds while the panel boots up.
- After the 55 second boot, LEDs 1 & 2 and 3 & 4 to alternately flash ON/OFF
- Within 10 seconds after the above pattern starts, change switch 1 to OFF
- All LED's will be off for several seconds seconds and then LEDs 1 & 4 will flash for about 3 seconds indicating the erase process has completed.
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